1. Field of the Invention
The present invention relates to nonvolatile memory devices, and more particularly to an improved nonvolatile memory based on floating gate transistors having fast pre-programming and erasing techniques.
2. Description of Related Art
Flash memory is a class of nonvolatile memory integrated circuits, based on floating gate transistors. The memory state of a floating gate cell is determined by the concentration of charge trapped in the floating gate. The operation of flash memory is largely dependent on the techniques used for injecting or removing charge from the floating gate.
There are at least two basic techniques utilized for moving charge into and out of floating gates of memory cells in flash memory. A first technique is referred to as hot electron injection. Hot electron injection is induced by applying a positive voltage between the drain and source of the memory cell, and a positive voltage to the control gate. This induces a current in the cell, and hot electrons in the current are injected through the tunnel oxide of the floating gate cell into the floating gate. Hot electron injection is a relatively quick, but high current operation; and therefore is usually limited to use for programming a few cells at a time in the device.
A second major technique for moving charge into and out of the floating gates of flash memory cells is referred to as Fowler-Nordheim tunneling (F-N tunneling). F-N tunneling is induced by establishing a large electric field between the control gate and one of the drain, source, and channel or between the control gate and a combination of these terminals. The electric field establishes a F-N tunneling current through the tunnel oxide and can be used for both injecting electrons into the floating gate, and driving electrons out of the floating gate. The F-N tunneling process is relatively low-current, because it does not involve a current flowing between the source and drain of the cells. Thus, it is commonly used in parallel across a number of cells at a time on a device.
Operation of flash memory involves programming the array, which requires a cell-by-cell control of the amount of charge stored in the floating gates, and erasing by which an entire array or a sector of the array is cleared to a predetermined charge state in the floating gates. In one kind of flash memory, F-N tunneling is used both for programming and for erasing cells in the array. In a second kind of flash memory, hot electron injection is used for programming and F-N tunneling is used for erasing.
In order to erase floating gate memory cells, and to insure a more uniform distribution of charge in the erased cells, a pre-programming sequence is carried out in conventional systems. Thus, all cells in a block to be erased, are pre-programmed to a known state, such as a high threshold state, prior to applying the erasing potentials. In this way, when the chip is erased, all of the memory cells will start with substantially the same amount of charge in the floating gate. Thus, the erasing sequence results in a more uniform charge levels across the entire block being erased.
However, the pre-programming stage in a chip or sector erase operation takes a substantial amount of time, according to conventional techniques. For example, each byte in the block to be erased must be pre-programmed, and then the success of the pre-programming needs to be verified. Only after the entire block to be erased has been pre-programmed and verified, can the erase operation occur.
In conventional approaches, the pre-programming has involved a byte-by-byte, or word-by-word programming operation, followed by byte-by-byte or word-by-word verifying. It can be appreciated that in order to pre-program and verify a large block of floating gate cells, substantial amount of time is involved.
For a discussion of the pre-programming techniques, see U.S. Pat. No. 5,563,822 entitled Fast Flash EPROM Programming and Pre-Programming Circuit Design and the references cited therein.
Accordingly, it is desirable to provide a flash memory cell design and operating technique which increases the speed of pre-programming of a floating gate memory array, in order to improve the overall performance of the device. Furthermore, it is desirable that the flash memory operating technique be suitable for low supply voltages.